1. Field of the Invention
The invention relates to integrated circuit design generally, and more particularly to Complementary Metal Oxide Semiconductor (CMOS) high performance, complex logic structures.
2. Background
Advances in semiconductor process technology and digital system architecture have led to requirements for integrated circuits to have increased operating frequencies. Unfortunately, higher operating frequencies result in undesirable increases in power consumption. Power consumption is a significant problem in integrated circuit design generally, and particularly in large, high speed products such as processors and microprocessors.
Circuit topologies such as clocked domino and differential cascode voltage switch (DCVS) logic have been developed to reduce the power otherwise consumed by conventional static logic.
Nonetheless, the trend of integrating more function on a single substrate while operating at ever higher frequencies goes on unabated.
What is needed is a circuit topology suitable for high speed operation while consuming less power than clocked domino or DCVS logic topologies.